cmos i2c 2-wire bus 4k electrically erasable programmable rom 512 x 8 bit eeprom turbo ic, inc. 24C04 product introduction pin description description : the turbo ic 24C04 is a serial 4k eeprom fabricated with turbos proprietary, high reliability, high performance cmos technology. its 4k of memory is organized as 512 x 8 bits. the memory is configured as 32 pages with each page con- taining 16 bytes. this device offers significant advantages in low power applications. the turbo ic 24C04 uses the i2c addressing protocol and 2-wire serial interface which includes a bidirectional serial data bus synchronized by a clock. it offers a flexible byte write and a faster 16-byte page write. the turbo ic 24C04 is assembled in either a 8-pin pdip or 8-pin soic package. pin #1 is not connected (nc). pin #2 is the a1 device address input for the 24C04. pin #3 is the a2 device address input for the 24C04, such that a total of four 24C04 devices can be connected on a single bus. pin #4 is the ground (vss). pin #5 is the serial data (sda) pin used for bidirectional transfer of data. pin #6 is the serial clock (scl) input pin. pin #7 is the write protect (wp) pin used to protect hardware data. pin #8 is the power supply (vcc) pin. all data is serially transmitted in bytes (8 bits) on the sda bus. to access the turbo ic 24C04 (slave) for a read or write operation, the controller (master) issues a start condi- tion by pulling sda from high to low while scl is high. the master then issues the device address byte which consists of 1010 (a2) (a1) (b8) (r/w). the most significant bits (1010) are a device type code signifying an eeprom device. a1 and a2 are the device address select bits which has to match the a1 and a2 pin inputs on the 24C04 device. the b[8] bit is the most significant bit of the memory address. the read/ write bit determines whether to do a read or write operation. after each byte is transmitted, the receiver has to provide an acknowledge by pulling the sda bus low on the ninth clock cycle. the acknowledge is a handshake signal to the transmitter indicating a successful data transmission. features : ? power supply voltage single vcc for read and programming (vcc = 2.7 v to 5.5 v) ? low power (isb = 2a @ 5.5 v) ? i2c bus, 2-wire serial interface ? support byte write and page write (16 bytes) ? automatic page write operation (maximum 10 ms) internal control timer internal data latches for 16 bytes ? high reliability cmos technology with eeprom cell endurance : 1,000,000 cycles data retention : 100 y ears 1 serial clock (scl) the scl input synchronizes the data on the sda bus. it is used in conjunction with sda to define the start and stop conditions. it is also used in conjunction with sda to transfer data to and from the turbo ic 24C04. serial data (sda) sda is a bidirectional pin used to transfer data in and out of the turbo ic 24C04. the pin is an open-drain output. a pullup resistor must be con- nected from sda to vcc. pin description device address (a1 & a2) a1 and a2 are device address inputs that en- ables a total of four 24C04 devices to connect on a single bus. when the address input pin is left unconnected, it is interpreted as zero. write protect (wp) when the write protect input is connected to vcc, the entire memory array is protected against write operations. for normal write operations, the write protect pin should be grounded. when the pin is left unconnected, wp is interpreted as zero. 1 2 3 4 5 6 7 8 nc a1 a2 gnd vcc wp scl sda 8 pin pdip 1 2 3 4 5 6 7 8 nc a1 a2 gnd vcc wp scl sda 8 pin soic
24C04 product introduction turbo ic, inc. note: the write cycle time t wc is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle. description (continued): for a write operation, the master issues a start condition, a device address byte, a memory address byte, and then up to 16 data bytes. the turbo ic 24C04 acknowledges after each byte transmission. to terminate the transmission, the master issues a stop condition by pulling sda from low to high while scl is high. for a read operation, the master issues a start condition and a device address byte. the turbo ic 24C04 acknowledges, and then transmits a data byte, which is accessed from the eeprom memory. the master acknowledges, indicating that it requires more data bytes. the turbo ic 24C04 transmits more data bytes, with the memory address counter auto- matically incrementing for each data byte, until the master does not acknowledge, indicating that it is terminating the transmission. the master then issues a stop condition. device operation: bidirectional bus protocol: the turbo ic 24C04 follows the i2c bus protocol. the proto- col defines any device that sends data onto the sda bus as a transmitter, and the receiving device as a receiver. the device controlling the transfer is the master and the device being controlled is the slave. the master always initiates the data transfers, and provides the clock for both transmit and receive operations. the turbo ic 24C04 acts as a slave de- vice in all applications. either the master or the slave can take control of the sda bus, depending on the requirement of the protocol. start/stop condition and data transitions: while scl clock is high, a high to low transition on the sda bus is recognized as a start condition which precedes any read or write operation. while scl clock is high, a low to high transition on the sda bus is recognized as a stop con- dition which terminates the communication and places the turbo ic 24C04 into standby mode. all other data transitions on the sda bus must occur while scl clock is low to ensure proper operation. acknowledge: all data is serially transmitted in bytes (8 bits) on the sda bus. the acknowledge protocol is used as a handshake sig- nal to indicate successful transmission of a byte of data. the bus transmitter, either the master or the slave (turbo ic 24C04), releases the bus after sending a byte of data on the sda bus. the receiver pulls the sda bus low during the ninth clock cycle to acknowledge the successful transmission of a byte of data. if the sda is not pulled low during the ninth clock cycle, the turbo ic 24C04 terminates the data trans- mission and goes into standby mode. for the write operation, the turbo ic 24C04 acknowledges after the device address byte, acknowledges after the memory address byte, and acknowledges after each subsequent data byte. for the read operation, the turbo ic 24C04 acknowledges after the device address byte. then the turbo ic 24C04 trans- mits each subsequent data byte, and the master acknowl- edges after each data byte transfer, indicating that it requires more data bytes. the turbo ic 24C04 monitors the sda bus for the acknowledge. to terminate the transmission, the mas- ter does not acknowledge, and then sends a stop condition. write cycle timing scl sda word n 8th bit ack stop condition start condition t wc 2
24C04 product introduction data valid turbo ic, inc. start and stop definition output acknowledge sda scl data stable data stable data change sda scl start stop scl data in data out 189 acknowledge start 3
24C04 product introduction turbo ic, inc. device addressing: following the start condition, the master will issue a device address byte consisting of 1010 (a2) (a1) (b8) (r/w) to ac- cess the selected turbo ic 24C04 for a read or write opera- tion. a1 and a2 are the device address select bits which have to match the a1 and a2 pin inputs on the 24C04 device. the b[8] bit is the most significant bit of the memory address. the (r/w) bit is a high (1) for read and low (0) for write. data input during write operation: during the write operation, the turbo ic 24C04 latches the sda bus signal on the rising edge of the scl clock. data output during read operation: during the read operation, the turbo ic 24C04 serially shifts the data onto the sda bus on the falling edge of the scl clock. memory addressing: the memory address is sent by the master in the form of 2 bytes. device address a2 and memory address bits b[8], are included in the device address byte. the remaining memory address bits b[7:0] are included in the second byte. the memory address byte can only be sent as part of a write operation. byte write operation: the master initiates the byte write operation by issuing a start condition, followed by the device address byte 1010 (a2) (a1) (b8) 0, followed by the memory address byte, fol- lowed by one data byte, followed by an acknowledge, then a stop condition. after each byte transfer, the turbo ic 24C04 acknowledges the successful data transmission by pulling the sda bus low. the stop condition starts the internal eeprom write cycle, and all inputs are disabled until the completion of the write cycle. 4 page write operation: the master initiates the page write operation by issuing a start condition, followed by the device address byte 1010 (a2) (a1) (b8) 0, followed by the memory address byte, fol- lowed by up to 16 data bytes, followed by an acknowledge, then a stop condition. after each byte transfer, the turbo ic 24C04 acknowledges the successful data transmission by pulling sda low. after each data byte transfer, the memory address counter is automatically incremented by one. the stop condition starts the internal eeprom write cycle only if the stop condition occurs in the clock cycle immediately fol- lowing the acknowledge (10th clock cycle). all inputs are dis- abled until the completion of the write cycle. polling acknowledge: during the internal write cycle of a write operation in the turbo ic 24C04, the completion of the write cycle can be detected by polling acknowledge. the master starts acknowledge poll- ing by issuing a start condition, then followed by the device address byte 1010 (a2) (a1) (b8) 0. if the internal write cycle is finished, the turbo ic 24C04 acknowledges by pulling the sda bus low. if the internal write cycle is still ongoing, the turbo ic 24C04 does not acknowledge because its inputs are disabled. therefore, the device will not respond to any command. by using polling acknowledge, the system delay for write operations can be reduced. otherwise, the system needs to wait for the maximum internal write cycle time, twc, given in the spec. power on reset: the turbo ic 24C04 has a power on reset circuit (por) to prevent data corruption and accidental write operations dur- ing power up. on power up, the internal reset signal is on and the turbo ic 24C04 will not respond to any command until the vcc voltage has reached the por threshold value.
24C04 product introduction turbo ic, inc. device address byte write sda line device address word address data s t o p a c k a c k m s b l s b r / w a c k s t a r t w r i t e page write sda line device address word address data (n) s t o p a c k a c k m s b l s b r / w a c k s t a r t w r i t e a c k // // data (n + x) 5
24C04 turbo ic, inc. random read current address read: the internal memory address counter of the turbo ic 24C04 contains the last memory address accessed during the pre- vious read or write operation, incremented by one. to start the current address read operation, the master issues a start condition, followed by the device address byte 1010 (a2) (a1) (b8) 1. the turbo ic 24C04 responds with an acknowledge by pulling the sda bus low, and then serially shifts out the data byte accessed from memory at the location correspond- ing to the memory address counter. the master does not acknowledge, then sends a stop condition to terminate the read operation. it is noted that the memory address counter is incremented by one after the data byte is shifted out. random address read: the master starts with a dummy write operation (one with no data bytes) to load the internal memory address counter by first issuing a start condition, followed by the device address byte 1010 (a2) (a1) (b8) 0, followed by the memory address bytes. following the acknowledge from the turbo ic 24C04, the master starts the current read operation by issuing a start condition, followed by the device address byte 1010 (a2) (a1) (b8) 1. the turbo ic 24C04 responds with an acknowledge by pulling the sda bus low, and then seri- ally shifts out the data byte accessed from memory at the location corresponding to the memory address counter. the master does not acknowledge, then sends a stop condition to terminate the read operation. it is noted that the memory address counter is incremented by one after the data byte is shifted out. sequential read: the sequential read is initiated by either a current address read or random address read. after the turbo ic 24C04 seri- ally shifts out the first data byte, the master acknowledges by pulling the sda bus low, indicating that it requires addi- tional data bytes. after the data byte is shifted out, the turbo ic 24C04 increments the memory address counter by one. then the turbo ic 24C04 shifts out the next data byte. the sequential reads continues for as long as the master keeps acknowledging. when the memory address counter is at the last memory location, the counter will roll-over when incremented by one to the first location in memory (address zero). the master terminates the sequential read operation by not acknowledging, then sends a stop condition. current address read sda line device address s t o p n o a c k m s b l s b r / w a c k s t a r t r e a d data product introduction 6 sda line device address data n s t o p n o a c k a c k a c k m s b l s b r / w a c k s t a r t w r i t e // // r e a d device address word address n dummy write
24C04 turbo ic, inc. sequential read sda line device address data n data n +1 data n + 2 s t o p a c k a c k a c k m s b l s b r / w a c k s t a r t r e a d n o a c k data n + 3 d.c. characteristics symbol parameter condition min max units i cc1 active vcc current read at 100 khz 1.0 ma i cc2 active vcc current write at 100 khz 3.0 ma i sb1 standby current vcc = 4.5 v 2.0 ua vcc = 5.5 v 2.0 ua i il input leakage current vin=vcc max 3 ua i ol output leakage current 3 ua v il input low voltage -1.0 0.8 v v ih input high voltage vccx0.7 vcc+0.5 v v ol1 output low vcc=4.5v iol=2.1 ma 0.4 v * absolute maximum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sec- tion of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. temperature storage: -65 c to 150 c under bias: -55 c to 125 c all input or output voltages with respect to vss +6 v to -0.3 v recommended operating conditions temperature range : commercial: 0 c to 70 c industrial: -40 c to 85 c military: -55 c to 125 c vcc supply voltage : 2.7 to 5.5 volts endurance: 100,000 cycles/byte (typical) data retention : 100 years product introduction absolute maximum ratings 7
24C04 turbo ic, inc. 2365 paragon drive, suite i, san jose, ca 95131 phone: 408-392-0208 fax: 408-392-0207 see us at www.turbo-ic.com rev. 4.0-10/28/01 turbo ic products and documents 1. all documents are subject to change without notice. please contact turbo ic for the latest revision of documents. 2. turbo ic does not assume any responsibility for any damage to the user that may result from accidents or operation under abnormal conditions. 3. turbo ic does not assume any responsibility for the use of any circuitry other than what embodied in a turbo ic product. no other circuits, patents, licenses are implied. 4. turbo ic products are not authorized for use in life support systems or other critical systems where component failure may endanger life. system designers should design with error detection and correction, redundancy and back-up features. turbo ic, inc. bus timing t su.sta t hd.sta t f t low t high t low t hd.dat t su.dat t r t su.sto t buf t dh t aa scl sda in sda out part numbers & order information tu24C04bs3i 512 x 8 serial eeprom product introduction a.c. characteristics symbol parameter 2.7 volt 5.5 volt min max min max units scl scl clock frequency 100 400 khz t noise suppression time (1) 100 50 ns t low clock low period 4.7 1.2 us t high clock high period 4.0 0.6 us t aa scl low to sda data out 0.1 4.5 0.1 0.9 us t buf bus free to new start (1) 4.7 1.2 us t hd.sta start hold time 4.0 0.6 us t su.sta start set-up time 4.7 0.6 us t hd.dat data-in hold time 0 0 us t su.dat data-in set-up time 200 100 ns t r scl and sda rise time (1) 1.0 0.3 us t f scl and sda fall time (1) 300 300 ns t su.sto stop set-up time 4.7 0.6 us t dh data-out hold time 100 50 ns t wc write cycle time 10 10 ms note: 1 this parameter is characterized and not 100% tested. temperature -commercial i -industrial package p -pdip s -soic voltage 3 - 2.7v to 5.5v - 4.5v to 5.5 v 2nd generation
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